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preliminary datasheet 1 5.00 hys64/72d32000gu / hys64/72d64020gu 2.5 v 184-pin unbuffered ddr-i sdram modules 256mb & 512mb modules preliminary datasheet rev. 0.9 the hys64/72d000gu are industry standard 184-pin 8-byte dual in-line memory modules (dimms) organized as 32m 64 and 64m 64 for non-parity and 32m x 72 and 64m x 72 for ecc main memory applications. the memory array is designed with double data rate synchronous drams (2.5v ddr-i). a variety of decoupling capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. ? 184-pin unbuffered 8-byte dual-in-line ddr-i sdram non-parity and ecc-modules for pc and server main memory applications ? one bank 32m 64, 32m x 72 and two bank 64m x 64, 64m 72 organization ? jedec standard double data rate synchronous drams (ddr-i sdram) single + 2.5 v ( 0.2 v) power supply ? built with 256mbit ddr-i sdrams in 66- lead tsopii package ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? all inputs and outputs sstl_2 compatible ? serial presence detect with e 2 prom ? jedec standard mo-206a form factor: 133.35 mm 31.75 mm 4.00 mm ? jedec standard reference layout ? gold plated contacts ? performance: -7 -7.5 -8 unit component speed grade pc266a pc266b pc200 module speed grade pc2100 pc2100 pc1600 f ck clock frequency (max.) @ cl = 2.5 143 133 125 mhz f ck clock frequency (max.) @ cl = 2 133 100 100 mhz
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 2 5.00 note: all part numbers end with a place code (not shown), designating the silicon-die revision. reference information available on request. example: hys 72d32000gu-8-a, indicating rev.a die are used for sdram components. ordering information type compliance code description sdram technology pc266a : hys64d32000gu-7 pc266a-20330-b1 one bank 256 mb reg. dimm 256 mbit hys72d32000gu-7 pc266a-20330-b1 one bank 256 mb reg. ecc-dimm 256 mbit hys64d64020gu-7 pc266a-20330-a1 two banks 512 mb reg. dimm 256 mbit HYS72D64020GU-7 pc266a-20330-a1 two banks 512 mb reg. ecc-dimm 256 mbit pc266b: hys64d32000gu-7.5 pc266b-25330-b1 one bank 256 mb reg. dimm 256 mbit hys72d32000gu-7.5 pc266b-25330-b1 one bank 256 mb reg. ecc-dimm 256 mbit hys64d64020gu-7.5 pc266b-25330-a1 two banks 512 mb reg. dimm 256 mbit HYS72D64020GU-7.5 pc266b-25330-a1 two banks 512 mb reg. ecc-dimm 256 mbit pc200r: hys64d32000gu-8 pc200-20220-b1 one bank 256 mb reg. dimm 256 mbit hys72d32000gu-8 pc200-20220-b1 one bank 256 mb reg. ecc-dimm 256 mbit hys64d64020gu-8 pc200-20220-a1 two banks 512 mb reg. dimm 256 mbit HYS72D64020GU-8 pc200-20220-a1 two banks 512 mb reg. ecc-dimm 256 mbit
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 3 5.00 pin definitions and functions a0 - a12 address inputs s0, s1 chip selects ba0, ba1 bank selects v dd power (+ 2.5 v) dq0 - dq63 data input/output v ss ground cb0 - cb7 check bits (x72 organization only) v ddq i/o driver power supply ras row address strobe v ddid vdd indentification flag cas column address strobe v ref i/o reference supply we read/write input v ddspd serial eeprom power supply cke0 - cke1 clock enable scl serial bus clock dqs0 - dqs8 sdram low data strobes sda serial bus data line clk0 - clk2, sdram clock (positive lines) sa0 - sa2 slave address select clk0 - clk2 sdram clock (negative lines) nc no connect dm0 - dm8 dqs9 - dqs17 sdram low data mask/ high data strobes address format density organization memory banks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 256 mb 32m x 64 1 32m x 8 8 13/2/10 8k 64 ms 7.8 m s 256 mb 32m x 72 1 32m x 8 9 13/2/10 8k 64 ms 7.8 m s 512 mb 64m 64 2 32m x 8 16 13/2/10 8k 64 ms 7.8 m s 512 mb 64m 72 2 32m x 8 18 13/2/10 8k 64 ms 7.8 m s
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 4 5.00 pin configuration frontside frontside backside backside pin# symbol pin# symbol pin# symbol pin# symbol 1 vref 48 a0 93 vss 140 nc / dm8/dqs17 2 dq0 49 nc / cb2 94 dq4 141 a10 3 vss 50 vss 95 dq5 142 nc / cb6 4 dq1 51 nc / cb3 96 vddq 143 vddq 5 dqs0 52 ba1 97 dm0/dqs9 144 nc / cb7 6dq2 key 98 dq6 key 7 vdd 53 dq32 99 dq7 145 vss 8 dq3 54 vddq 100 vss 146 dq36 9 nc 55 dq33 101 nc 147 dq37 10 nc 56 dqs4 102 nc 148 vdd 11 vss 57 dq34 103 a13 149 dm4/dqs13 12 dq8 58 vss 104 vddq 150 dq38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 vss 15 vddq 61 dq40 107 dm1/dqs10 153 dq44 16 clk1 62 vddq 108 vdd 154 ras 17 clk1 63 we 109 dq14 155 dq45 18 vss 64 dq41 110 dq15 156 vddq 19 dq10 65 cas 111 cke1 157 s0 20 dq11 66 vss 112 vddq 158 s1 21 cke0 67 dqs5 113 nc (ba2) 159 dm5/dqs14 22 vddq 68 dq42 114 dq20 160 vss 23 dq16 69 dq43 115 a12 161 dq46 24 dq17 70 vdd 116 vss 162 dq47 25 dqs2 71 nc 117 dq21 163 nc 26 vss 72 dq48 118 a11 164 vddq 27 a9 73 dq49 119 dm2/dqs11 165 dq52 28 dq18 74 vss 120 vdd 166 dq53 29 a7 75 clk2 121 dq22 167 nc 30 vddq 76 clk2 122 a8 168 vdd 31 dq19 77 vddq 123 dq23 169 dm6/dqs15 32 a5 78 dqs6 124 vss 170 dq54 33 dq24 79 dq50 125 a6 171 dq55 34 vss 80 dq51 126 dq28 172 vddq 35 dq25 81 vss 127 dq29 173 nc 36 dqs3 82 vddid 128 vddq 174 dq60 37 a4 83 dq56 129 dm3/dqs12 175 dq61 38 vdd 84 dq57 130 a3 176 vss 39 dq26 85 vdd 131 dq30 177 dm7/dqs16 40 dq27 86 dqs7 132 vss 178 dq62 41 a2 87 dqs8 133 dq31 179 dq63 42 vss 88 dq59 134 nc / cb4 180 vddq 43 a1 89 vss 135 nc / cb5 181 sa0 44 nc / cb0 90 nc 136 vddq 182 sa1 45 nc / cb1 91 sda 137 ck0 183 sa2 46 vdd 92 scl 138 ck0 184 vddspd 47 nc / dqs8 139 vss note: pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are nc (no-connects) on x64 organised non-ecc modules
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 5 5.00 block diagram: one bank 32m 64 ddr-i sdram dimm module hys64d32000gu using x8 organized sdrams on raw card version b dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0/dqs9 i/o 5 i/o 4 i/o 3 i/o 2 dq12 dq13 dq14 dq8 dq9 dq10 dq1 1 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 i/o 5 i/o 4 i/o 3 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 i/o 5 i/o 4 i/o 3 i/o 2 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 i/o 5 i/o 4 i/o 3 i/o 2 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4/dqs13 i/o 5 i/o 4 i/o 3 i/o 2 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 i/o 5 i/o 4 i/o 3 i/o 2 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 i/o 5 i/o 4 i/o 3 i/o 2 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 i/o 5 i/o 4 i/o 3 i/o 2 dm7/dqs16 a0 - a12 a0 - a12: sdrams d0 - d7 a0 ser ial pd a1 a2 sa0 sa1 sa2 scl sda ras ras : sdrams d0 - d7 cas cas : sdrams d0 - d7 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d7 s 0 s s s s s s s s ba0 - ba1 ba0, ba1: sdrams d0 - d7 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 2 dqs dqs dqs dqs notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 2 sdrams 3 sdrams 3 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 v dd v ss d0 - d7 d0 - d7 v ddq d0 - d7 d0 - d7 vref v ddid
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 6 5.00 block diagram: two bank 64m 64 ddr-i sdram dimm modules hys64d64020gu using x8 organized sdrams on raw card version a dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0/dqs9 dm d8 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq12 dq13 dq14 dq8 dq9 dq10 dq1 1 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 dm d9 i/o 5 i/o 4 i/o 3 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 dm d10 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 dm d1 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4/dqs13 dm d12 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 dm d13 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 dm d14 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 dm d15 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm7/dqs16 a0 - a12 a0 - a12: sdrams d0 - d15 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda ras ras : sdrams d0 - d15 cas cas : sdrams d0 - d15 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d15 s 0 s 1 s s s s s s s s s s s s s s s s cke1 cke: sdrams d8 - d15 ba0, ba1 ba0, ba1: sdrams d0, d15 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 2 i/o 5 dqs dqs dqs dqs dqs dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 4 sdrams 6 sdrams 6 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 v dd v ss d0 - d15 d0 - d15 v ddq d0 - d15 d0 - d15 vref notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq v ddid
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 7 5.00 block diagram: one bank 32m 72 ddr-i sdram dimm module hys72d32000gu using x8 organized sdrams on raw card version b dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0/dqs9 i/o 5 i/o 4 i/o 3 i/o 2 dq12 dq13 dq14 dq8 dq9 dq10 dq1 1 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 i/o 5 i/o 4 i/o 3 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 i/o 5 i/o 4 i/o 3 i/o 2 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 i/o 5 i/o 4 i/o 3 i/o 2 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4/dqs13 i/o 5 i/o 4 i/o 3 i/o 2 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 i/o 5 i/o 4 i/o 3 i/o 2 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 i/o 5 i/o 4 i/o 3 i/o 2 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 i/o 5 i/o 4 i/o 3 i/o 2 dm7/dqs16 a0 - a12 a0 - a12: sdrams d0 - d8 a0 ser ial pd a1 a2 sa0 sa1 sa2 scl sda ras ras : sdrams d0 - d8 cas cas : sdrams d0 - d8 cke0 cke: sdrams d0 - d8 we we : sdrams d0 - d8 s 0 s s s s s s s s ba0, ba1 ba0, ba1: sdrams d0 - d8 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 2 dqs dqs dqs dqs notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 3 sdrams 3 sdrams 3 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 v dd v ss d0 - d8 d0 - d8 v ddq d0 - d8 d0 - d8 vref v ddid dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d8 i/o 5 i/o 4 i/o 3 i/o 2 dm8/dqs17 s dqs8 dqs
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 8 5.00 block diagram: two bank 64m 72 ddr-i sdram dimm modules HYS72D64020GU using x8 organized sdrams on raw card version a dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0/dqs9 dm d9 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq12 dq13 dq14 dq8 dq9 dq10 dq1 1 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 dm d10 i/o 5 i/o 4 i/o 3 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 dm d11 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 dm d1 2 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4/dqs13 dm d13 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 dm d14 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 dm d15 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 dm d16 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm7/dqs16 a0 - a12 a0 - a12: sdrams d0 - d17 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda ras ras : sdrams d0 - d17 cas cas : sdrams d0 - d17 cke0 cke: sdrams d0 - d8 we we : sdrams d0 - d17 s 0 s 1 s s s s s s s s s s s s s s s s cke1 cke: sdrams d9 - d17 ba0, ba1 ba0, ba1: sdrams d0 - d17 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 2 i/o 5 dqs dqs dqs dqs dqs dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 6 sdrams 6 sdrams 6 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 v dd v ss d0 - d17 d0 - d17 v ddq d0 - d17 d0 - d17 vref notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq v ddid dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 dm d1 2 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm8/dqs17 s s dqs8 dqs dqs
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 9 5.00 capacitance (target, not verified) t a = 0 to 70 c; v dd =2.5v 0.2 v, f =1mhz parameter symbol limit values (max.) unit one bank modules two bank modules input capacitance (all inputs except clk,clk & cke) c in tbd. tbd. pf input capacitance (clk, clk ) c clk tbd. tbd. pf input capacitance (cke) c cke tbd. tbd. pf input/output capacitance (dq0 - dq63, cb0 - cb7) c io tbd. tbd. pf input capacitance (scl, sa0 - 2) c sc 88pf input/output capacitance (sda) c sd 88pf 6 dram loads 4 dram l oa d s 3 dr am l oa d s 2 dram l oa d s clock net wiring
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 10 5.00 supply voltage levels parameter symbol limit values unit notes min. nom. max. device supply voltage v dd 2.3 2.5 2.7 v C output supply voltage v ddq 2.3 2.5 2.7 v 1) input reference voltage v ref 1.15 1.25 1.35 v 2) termination voltage v tt v ref C0.04 v ref v ref +0.04 v 3) 1) under all conditions, v ddq must be less than or equal to v dd . 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . 3) v tt of the transmitting device must track v ref of the receiving device. dc operating conditions (sstl_2 inputs) ( v ddq =2.5v, t a =70 c, voltage referenced to v ss ) parameter symbol limit values unit notes min. max. dc input logic high v ih (dc) v ref +0.18 v ddq +0.3 v 1) dc input logic low v il (dc) C 0.30 v ref C0.18 v C input leakage current i il C 5 5 m a 2) output leakage current i ol C 5 5 m a 2) 1) the relationship between the v ddq of the driving device and the v ref of the receiving device is what determines noise margins. however, in the case of v ih (max) (input overdrive), it is the v ddq of the receiving device that is referenced. in the case where a device is implemented such that it supports sstl_2 inputs but has no sstl_2 outputs (such as a translator), and therefore no v ddq supply voltage connection, inputs must tolerate input overdrive to 3.0 v (high corner v ddq +300mv). 2) for any pin under test input of 0 v v in v ddq +0.3v. operating, standby and refresh currents (for reference only) (values apply to one sdram component and do not include register and pll) ( t a = 0 to +70 c, v dd =2.5v0.2v) parameter symbol test condition speed unit notes C 7 C 7.5 C 8 operating current t rc = t rc(min) , t ck = min. active-precharge command without burst operation i cc1 1 bank operation cas latency = 2 100 90 70 ma 1), 2), 3) precharge standby current in power down mode i cc2p cke v il(max) , t ck = min., cs = v ih(min) 20 20 20 ma 1)
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 11 5.00 precharge standby current in non-power down mode i cc2n cke 3 v ih(min) , t ck = min., cs = v ih (min) 50 45 40 ma 1), 3) no operating current (active state: 4 bank) i cc3p cke v il(max) , t ck = min. 30 30 30 ma 1) i cc3n cke 3 v ih(min) , t ck = min., cs = v ih (min) 65 60 55 ma 1), 3) operating current (burst mode) i cc4 t ck = min., read/write command cycling, multiple banks active, gapless data, bl = 4 140 120 100 ma 1), 2), 3) auto (cbr) refresh current i cc5 t ck = min., t rc = t rfc(min) cbr command cycling 155 135 110 ma 1), 4), 5) self refresh current i cc6 cke 0.2v 111ma 1), 4) 1) these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t ck and t rc . 2) the specified values are obtained with the output open. 3) input signals are changed once during three clock cycles. 4) 8192 refresh cycles in 64 ms. 5) minimum cycle time during auto refresh operation ( t ref ) is greater than minimum cycle time for read/write operation. operating, standby and refresh currents (contd) (for reference only) (values apply to one sdram component and do not include register and pll) ( t a = 0 to +70 c, v dd =2.5v0.2v) parameter symbol test condition speed unit notes C 7 C 7.5 C 8
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 12 5.00 ac characteristics (for reference only) (values apply to the sdram component and do not include register, pll, or card wiring) ( t a =0 to+70 c, v dd =2.5v0.2v) parameter symbol -7 pc266a -7.5 pc266b -8 pc200 unit notes min. max. min. max. min. max. dq output access time from ck/ ck t ac C 0.75 + 0.75 C 0.75 + 0.75 C 0.8 + 0.8 ns C dqs output access time from ck/ ck t dqsck C 0.75 + 0.75 C 0.75 + 0.75 C 0.8 + 0.8 ns C clk high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 *tck C clk low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 *tck C clock period cl = 2 t ck 7.52010201020ns 1) cl = 2.5 7 20 7.5 20 8 20 ns C cl=3 7207.520820nsC dq and dm input hold time t dh 0.5 C 0.5 C 0.6 C ns C dq and dm input setup time t ds 0.5 C 0.5 C 0.6 C ns C dq and dm input pulse width (for each input) t dipw 1.75C1.75C2CnsC data-out high-impedance from ck/ ck t hz C 0.75 + 0.75 C 0.75 + 0.75 C 0.8 + 0.8 ns C data-out low-impedance from ck/ ck t lz C 0.75 + 0.75 C 0.75 + 0.75 C 0.8 + 0.8 ns C dqs-dq skew t dqsq C+0.5C+0.5C+0.6nsC qh data-out hold time from dqs t qh thp-0.75 C thp-0.75 C thp-1.0 C ns 2) write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 * t ck C dqs input valid time t dsl,h 0.4 0.6 0.4 0.6 0.4 0.6 * t ck C mode register/extended mode register set cycle time t mrd 15C15C16CnsC write preamble setup time t wpres 0C0C0CnsC dqs hold time from ck/ck t wpreh 0.25 C 0.25 C 0.25 C * t ck C write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 * t ck C input setup time (lvttl inputs) t is 0.9 C 0.9 C 1.2 C ns 3) input hold time (lvttl inputs) t ih 0.9 C 0.9 C 1.2 C ns 3) read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 * t ck C read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 * t ck C row active time t ras 45 120k 45 120k 50 120k ns C row cycle time r/w operation t rc 65C65C70CnsC auto refresh t rfc 75C75C80Cns 1) ras to cas delay t rcd 20C20C20CnsC row precharge time t rp 20C20C20CnsC row activate to row activate delay t rrd 15C15C15CnsC write recovery time t wr 15C15C15CnsC
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 13 5.00 auto precharge write recovery + precharge time t dal 35 C35C35CnsC internal write to read command delay t wtr 1C1C1C* t ck C power down entry time t pdent t is + 1 clk 2 clk + t is CC t is + 1 clk 2 clk + t is ns C power down exit time t pdex t is + 1 clk 2 clk + t is CC t is + 1 clk 2 clk + t is ns C self refresh exit time t srex 200C 200C 200C cyclesC average periodic refresh intercal t ref C7.8C7.8C7.8 m sC clk transition time t t 0.5CCC0.5CnsC 1) minimum auto refresh cycle time is greater than minimum cycle time during normal read or write operation. 2) t hp is the lesser of t cl and t ch 3) these parameters guarantee device timing, but they are not necessarily tested on each device they may be guaranteed by design or tester correlation t is / t ih =0.9ns for pc266 are measured with command / address input slew rate of > 1.0v/ns for command / address input slew rate of > 0.5v/ns and < 1.0v/ns t is / t ih = 1.0ns should be guaranteed by design for pc200 t is / t ih = 1.2ns command / address input slew rate of 1.0v/ns is assumed slew rate is measured between v oh (ac) and v ol (ac) ck / ck slew rates are assumed to be > 1.0v/ns pulse width for command / address signals to be properly sampled at rising edges of clock shall be a minimum of 2.2ns environmental parameters symbol parameter rating units notes t opr operating temperature (ambient) 0 to +55 o c h opr operating humidity (relative) 10 to 90 % t stg storage temperature -50 to +100 o c 1) h stg storage humidity (without condensation) 5 to 95 % 1) barometric pressure (operating and storage) 105 to 69 k pascal 2) 1) stresses greater than those listed may cause permanent damage to the device. device functional operation at or above these con ditions is not implied. 2) up to 3000 m (9850 ft) ac characteristics (contd) (for reference only) (values apply to the sdram component and do not include register, pll, or card wiring) ( t a =0 to+70 c, v dd =2.5v0.2v) parameter symbol -7 pc266a -7.5 pc266b -8 pc200 unit notes min. max. min. max. min. max.
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 14 5.00 package outlines simplified mechanical drawing (for details see jedec document mo-206a) ddr-i unbuffered dimm modules 31.75 19,8 133,35 128,93 10,0 17,8 2,3 2,175 6,62 1,8 detail a: b detail b: 64,77 49,53 92 93 pin 184 2,5 n/a for x64 n/a for x64 spd
hys64/72d32000gu / hys64/72d64020gu unbuffered ddr-i sdram-modules preliminary datasheet 15 5.00 change list 9.5.2000 rev.0.9 first target revision

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